NB3N51044DTG - 

The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL. NB3N51044 is configurable to bypass the PLL from signal path using BYPASS, and provides the output frequency through the divider network. All clock outputs can be individually enabled/disabled through hardware input pins OE[3:0]. In addition, device can be reset using Master Reset input pin MR_OE#.

Features:

Uses 25 MHz Fundamental Crystal or Reference Clock Input

Four Low Skew HCSL or LVDS Outputs

Output Frequency Selection of 100 MHz or 125 MHz

Individual OE Tri-States Outputs

Master Reset and BYPASS Modes

PCIe Gen 1, Gen 2, Gen 3 Compliant

Typical Phase Jitter @ 125 MHz (Integrated 1.875 MHz to 20 MHz): 0.2 ps

Typical Cycle-Cycle Jitter @ 100 MHz (10k cycles): 20 ps

Phase Noise @ 100 MHz: Offset Noise Power
100 Hz -101 dBc/Hz
1 kHz -123 dBc/Hz
10 kHz -133 dBc/Hz
100 kHz -136 dBc/Hz
1 MHz -141 dBc/Hz
10 MHz -155 dBc/Hz

Operating Supply Voltage Range 3.3 V ±5%

Industrial Temperature Range -40°C to +85°C

Functionally Compatible with ICS841604I with enhanced performance

These are Pb-Free Devices

Applications:

Networking

Consumer

Computing and Peripherals

Industrial Equipment

PCIe Clock Generation Gen 1, Gen 2 and Gen 3

End Products:

Switch and Router

Set Top Box, LCD TV

Servers, Desktop Computers

Automated Test Equipment